ADCH and ADCL - buffered?
if start , adc conversion, setting adsc bit in adcsra, , shortly thereafter (before conversion finished) read adcl , adch (in proper order),
a) completed result previous conversion
or
b) half-completed result current conversion?
a) completed result previous conversion
or
b) half-completed result current conversion?
this should help. from s26.3 atmega 1280 datasheet...
"if result left adjusted , no more 8-bit precision required, sufficient read
adch. otherwise, adcl must read first, adch, ensure content of data
registers belongs same conversion. once adcl read, adc access data registers
is blocked. means if adcl has been read, , conversion completes before adch is
read, neither register updated , result conversion lost. when adch read,
adc access adch , adcl registers re-enabled."
"if result left adjusted , no more 8-bit precision required, sufficient read
adch. otherwise, adcl must read first, adch, ensure content of data
registers belongs same conversion. once adcl read, adc access data registers
is blocked. means if adcl has been read, , conversion completes before adch is
read, neither register updated , result conversion lost. when adch read,
adc access adch , adcl registers re-enabled."
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